Design of Low Power Low Input Impedance CMOS Current Comparator

This paper presents the new design of a CMOS current comparator with ultra low input impedance, which especially benefits on enhancing the accuracy of pulse-width-modulation (PWM). The proposed design reduces the input impedance by utilizing common-gate structure as input stage. A novel low power with high performance low current comparator is proposed in this paper which comprises of low input impedance using a simple biasing method. The further use of a commonsource feedback structure also enables extremely reduction of the input impedance. In addition, the proposed design can be applied to perform precise comparison between two terminals with varied currents since the input impedances are well designed to be balanced. The experiment results demonstrate competitive performance. With input current of 25MHz square wave, the input impedance and of comparator are merely 57.2Ω while the average power consumption is about 9.08mW under the implementation of TSMC 0.35μm CMOS process with 3.3V power supply.