Quadrature direct digital frequency synthesizer using an angle rotation algorithm

Author

Curticapean, F. ; Palomaki, Kalle I. ; Niittylahti, Jarkko

Author_Institution

Inst. of Digital & Comput. Syst., Tampere Univ. of Technol., Finland

Volume

2

fYear

2003

fDate

25-28 May 2003

Abstract

In this paper, a quadrature direct digital frequency synthesizer (DDFS) based on a new angle rotation algorithm is presented. It is shown that the proposed architecture features higher spectral purity,, reduced hardware cost, power consumption, and tuning. latency when compared to previously presented designs. The introduced DDFS produces 16-bit sine and cosine waveforms with a spurious free dynamic range (SFDR) of 114 dBc. The design was implemented using a 0.35 μm CMOS technology. It occupies an area of 0.46 mm² and dissipates 115 mW at 3.3 V supply voltage and 100 MHz clock.

Keywords

CMOS digital integrated circuits; circuit tuning; direct digital synthesis; 0.35 micron; 100 MHz; 115 mW; 16 bit; 3.3 V; CMOS; angle rotation algorithm; cosine waveforms; hardware cost; power consumption; quadrature direct digital frequency synthesizer; sine waveforms; spectral purity; spurious free dynamic range; tuning latency; CMOS technology; Clocks; Costs; Delay; Dynamic range; Energy consumption; Frequency synthesizers; Hardware; Tuning; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on

Print_ISBN

0-7803-7761-3

Type

conf

DOI

10.1109/ISCAS.2003.1205895

Filename

1205895