Title :
HDTV level MPEG2 video decoder VLSI
Author :
Onoye, Takao ; Masaki, Toshihiro ; Morimoto, Yasuo ; Sato, Yoh ; Shirakawa, Isao
Author_Institution :
Dept. of Inf. Syst. Eng., Osaka Univ., Japan
Abstract :
A novel architecture for an HDTV level MPEG2 decoder is developed, which consists of specific functional macrocells and macroblock level pipeline buffers. Owing to the sophisticated I/O interface among macrocells, macroblock level pipeline buffers are successfully incorporated with functional macrocells. A new organization of frame memory and interface is also devised. The designed decoder contains 454 K transistors, and occupies 81.0 mm2 with a 0.6 μm triple-metal CMOS technology
Keywords :
CMOS digital integrated circuits; VLSI; decoding; digital signal processing chips; high definition television; video coding; 0.6 micron; HDTV level MPEG2 video decoder VLSI; I/O interface; architecture; frame memory; functional macrocells; macroblock level pipeline buffers; transistors; triple-metal CMOS technology; Application specific integrated circuits; CMOS technology; Decoding; Electronic mail; HDTV; Information systems; Macrocell networks; Pipelines; Very large scale integration; Workstations;
Conference_Titel :
Microelectronics and VLSI, 1995. TENCON '95., IEEE Region 10 International Conference on
Print_ISBN :
0-7803-2624-5
DOI :
10.1109/TENCON.1995.496442
