Implementation of a programmable 64∼2048-point FFT/IFFT processor for OFDM-based communication systems

Orthogonal Frequency Division Multiplexing (OFDM) system is famous for its robustness against frequency selective fading channel. The Fast Fourier Transform (FFT) and Inverse FFT (IFFT) processor ire used as the modulation/demodulation kernel in the OFDM systems. The sizes of FFT/IFFT processors are varied in the different applications of OFDM systems. In this paper, we design and implement a programmable 64∼2048-point FFT/IFFT processor to cover the different specifications of OFDM applications. The cached-memory architecture is our suggested VLSI system architecture. We implement the Processing Element (PE) by using CORDIC algorithm to replace the multiplier-based PE. We also proposed π/4-prerotation and modified EEAS-CORDIC VLSI architecture to reduce the iteration number and quantization noise. Finally, we implement the FFT processor with TSMC 0.35 μm IP4M CMOS technology. The die area of the FFT/IFFT processor is 12.25 mm² including 2048×32 bits memory. The input/output wordlength is 16-bit wide. The chip can operate under 80 MHz and meet most standard requirements (64∼2048 points).