• DocumentCode
    3537218
  • Title

    An efficient memory-based FFT architecture

  • Author

    Chang, Chao-Kai ; Hung, Chung-Ping ; Chen, Sau-Gee

  • Author_Institution
    Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
  • Volume
    2
  • fYear
    2003
  • fDate
    25-28 May 2003
  • Abstract
    This paper proposes an efficient memory-based radix-2 FFT architecture, which greatly improves the memory-based FFT by reducing 50% memory size requirement, while maintaining a simple address generator. Specifically the memory size is reduced to 1.25N words. In addition, the multiplier utilization rate is 100%.
  • Keywords
    VLSI; digital signal processing chips; fast Fourier transforms; performance evaluation; random-access storage; RAM; address generator; memory size requirement reduction; memory-based FFT architecture; multiplier utilization; radix-2 FFT architecture; Chaos; Maintenance engineering; Memory architecture; OFDM modulation; Parallel processing; Pipelines; Random access memory; Real time systems; Signal processing; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on
  • Print_ISBN
    0-7803-7761-3
  • Type

    conf

  • DOI
    10.1109/ISCAS.2003.1205910
  • Filename
    1205910
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3537218