DocumentCode
353808
Title
Switched bus in information system-principal and design
Author
Wang, Yanfang
Author_Institution
Fast Electron. Lab., Univ. of Sci. & Technol. of China, Hefei, China
Volume
4
fYear
2000
fDate
2000
Firstpage
2517
Abstract
Two kinds of bus architectures are compared. Because of bandwidth limitation of shared bus, it is the bottle-neck of system´s performance. Switched bus is more capable and scalable. In modem server and router, high-speed serial link and cross point switch is the current trend of technology. A prototype point-to-point 1.25 Bbps backplane is described, the BER of which is less then 1E-12
Keywords
system buses; bandwidth limitation; bus architectures; cross point switch; high-speed serial link; modem; router; server; shared bus; switched bus; Backplanes; Bandwidth; Bit error rate; Modems; Prototypes; Switches; System performance;
fLanguage
English
Publisher
ieee
Conference_Titel
Intelligent Control and Automation, 2000. Proceedings of the 3rd World Congress on
Conference_Location
Hefei
Print_ISBN
0-7803-5995-X
Type
conf
DOI
10.1109/WCICA.2000.862499
Filename
862499
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