Spin devices for integrated circuits

Author

Tanaka, M. ; Sugahara, S.

Author_Institution

Dept. of Electron. Eng., Tokyo Univ., Japan

fYear

2005

fDate

4-8 April 2005

Firstpage

1571

Lastpage

1572

Abstract

A spin MOSFET consisting of a MOS structure and half-metallic ferromagnetic contacts for source and drain was theoretically analyzed. A novel MRAM cell employing a single spin MOSFET is also proposed, which can realize ultimately high degree of device integration, a fast readout scheme with excellent fault tolerance and good compatibility with the well-established Si-MOSFET technology. Also, a novel reconfigurable logic gates employing spin MOSFETs was proposed and numerically simulated.

Keywords

MIS structures; MOSFET; ferromagnetic materials; magnetic storage; magnetoelectronics; random-access storage; MOS structure; MRAM cell; fast readout scheme; fault tolerance; half-metallic ferromagnetic contacts; integrated circuits; spin MOSFET; spin devices; CMOS logic circuits; Field programmable gate arrays; Logic devices; Logic functions; MOSFET circuits; Magnetization; Nonvolatile memory; Numerical simulation; Reconfigurable logic; Table lookup;

fLanguage

English

Publisher

ieee

Conference_Titel

Magnetics Conference, 2005. INTERMAG Asia 2005. Digests of the IEEE International

Print_ISBN

0-7803-9009-1

Type

conf

DOI

10.1109/INTMAG.2005.1464219

Filename

1464219

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3538165