A SEU-resistant, FPGA-based implementation of the substitution transformation in AES for security on satellites

Designing single event upset (SEU)-resistant security for communications in satellites is an important yet challenging problem. For example, although SRAM-based FPGAs are beneficial for satellite applications, they are susceptible to SEUs. Harsh environments such as space where cosmic radiation is present increase the likelihood of these errors known as SEUs. However these errors are also expected to be prevalent in non-space applications of future nanometer technologies. Thus this is an important problem to be studied for future secure embedded systems. Satellites require an encryption mechanism for many purposes; for example, to provide secure communications with the ground station. A SEU detection technique for a symmetric encryption algorithm, such as the NIST standardized Advanced Encryption Standard (AES), is additionally challenging due to its complex non-linear task in the algorithm, namely the substitution transformation (sub_byte). This research presents an efficient solution for single-bit SEU detection in the substitution task of AES. This approach uses fewer memory cells, provides 100% single-bit SEU coverage and achieves a low failure in time (FIT). This research is important for secure communications in an error-prone harsh environment such as satellites where low cost and high reliability are important.