Design of Intelligent Power Saving (IPS) architecture for reducing power and area in NoC

Author

Basha, S. Syed ; Babu, T. Ravichandra

Author_Institution

Dept. of ECE, AIET, Hyderabad, India

fYear

2015

fDate

19-20 March 2015

Firstpage

1

Lastpage

8

Abstract

The solution of data loss and deadlock in Network on Chip (NoC) is by using Virtual Channels. Most of the virtual channels included router of one input or output port. The power problem is extremely significant in virtual channels as the router includes five input-output ports. In this Paper, a new architecture proposed Intelligent Power Saving (IPS) for reducing power and area in virtual channels of NoC. The Proposed architecture can concert diverse considerations to reduce the power and optimization area in NoC. Compared to designs with IPS, in a given budget, we prove that reduces 37.31%, 45.79% and 19.26% in power and reduces 49.4%, 25.5% and 14.4% on area, respectively.

Keywords

integrated circuit layout; low-power electronics; network-on-chip; NoC; architecture proposed intelligent power saving; area reduction; intelligent power saving architecture; network router; network-on-chip; power problem; power reduction; virtual channel; Clocks; IP networks; Kernel; Nickel; Payloads; IPS; NoC; power reduction; virtual channels;

fLanguage

English

Publisher

ieee

Conference_Titel

Innovations in Information, Embedded and Communication Systems (ICIIECS), 2015 International Conference on

Conference_Location

Coimbatore

Print_ISBN

978-1-4799-6817-6

Type

conf

DOI

10.1109/ICIIECS.2015.7192791

Filename

7192791