Proceedings of EURO-DAC. European Design Automation Conference

The following topics were dealt with: system-level synthesis; information modelling; timing issues in synthesis; placement and routing; different aspects of testability improvements; architectural synthesis; partitioning and floorplanning; simulation and partitioning of hardware/ software systems; fault modeling and delay testing; analogue and timing modelling; ATPG and speed-up techniques; simulation and debugging of system descriptions; logic synthesis and optimization; framework architectures; hardware/software system design; EMC and thermal effects; new ideas in synthesis; simulation; formal methods; language development; behavioural synthesis from VHDL; design techniques; system-level design; modeling; and verification and validation