Implementation of vedic divider on RSA cryptosystem

RSA cryptosystem is an old and premier public key cryptography, which is used for data security. A divider is one of the key hardware blocks in most applications such as digital signal processing, cryptography and in other logical computations. Low power consumption, high speed and smaller area are some of the most important aspects for designing of any VLSI system. Area and speed are usually incompatible constraints. So good design has to set equilibrium between area and speed. It is also known fact that Divider unit forms an integral part of processor design. Due to this regard, high speed divider architecture becomes the need of the day. This paper deals with the implementation of vedic divider in RSA algorithm instead of conventional divider. Vedic mathematics describes a method called `Dhvajanka - On the top of flag´ which is a generalized formula for Vedic division used in vedic divider. Verilog code is programmed and simulated by Quartus II 9.0. Power dissipation has been reduced. Significant improvement has been observed in terms of area utilization and time delay.