Title :
Tree restructuring approach to mapping problem in cellular-architecture FPGAs
Author :
Ramineni, N. ; Chrzanowska-Jeske, M. ; Buddi, N.
Author_Institution :
Synopsys Inc., Beaverton, OR, USA
Abstract :
A new technique for mapping combinational circuits to fine-grain cellular-architecture FPGAs is presented. The proposed tree restructuring algorithm preserves local connectivity and allows direct mapping of the tree to the cellular array, thus eliminating the traditional routing phase. The developed bus assignment algorithm efficiently utilizes medium and long distance routing resources (buses). The method is general and can be used for any fine-grain cellular-architecture type FPGA. To demonstrate our techniques, the ATMEL 6000 series FPGA was used as a target architecture. The results are very encouraging
Keywords :
cellular arrays; field programmable gate arrays; programmable logic arrays; ATMEL 6000 series FPGA; bus assignment algorithm; cellular-architecture FPGAs; direct mapping; local connectivity; mapping problem; tree restructuring approach; Circuit synthesis; Costs; Design automation; Electronics packaging; Field programmable gate arrays; Logic arrays; Logic devices; Phased arrays; Routing; Shape;
Conference_Titel :
Design Automation Conference, 1995, with EURO-VHDL, Proceedings EURO-DAC '95., European
Conference_Location :
Brighton
Print_ISBN :
0-8186-7156-4
DOI :
10.1109/EURDAC.1995.527390