DocumentCode :
3539794
Title :
MACAU: A Markov model for reliability evaluations of caches under Single-bit and Multi-bit Upsets
Author :
Suh, Jinho ; Annavaram, Murali ; Dubois, Michel
Author_Institution :
Ming Hsieh Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
fYear :
2012
fDate :
25-29 Feb. 2012
Firstpage :
1
Lastpage :
12
Abstract :
Due to the growing trend that a Single Event Upset (SEU) can cause spatial Multi-Bit Upsets (MBUs), the effects of spatial MBUs has recently become an important yet very challenging issue, especially in large, last-level caches (LLCs) protected by protection codes. In the presence of spatial MBUs, the strength of the protection codes becomes a critical design issue. Developing a reliability model that includes the cumulative effects of overlapping SBUs, temporal MBUs and spatial MBUs is a very challenging problem, especially when protection codes are active. In this paper, we introduce a new framework called MACAU. MACAU is based on a Markov chain model and can compute the intrinsic MTTFs of scrubbed caches as well as benchmark caches protected by various codes. MACAU is the first framework that quantifies the failure rates of caches due to the combined effects of SBUs, temporal MBUs and spatial MBUs.
Keywords :
Markov processes; cache storage; integrated circuit reliability; MACAU; Markov chain model; cache reliability evaluations; last-level caches; multibit upsets; overlapping SBU; protection codes; single event upset; single-bit upsets; spatial MBU; temporal MBU; Benchmark testing; Clocks; Computational modeling; Random access memory; Reliability engineering; Single event upset;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
High Performance Computer Architecture (HPCA), 2012 IEEE 18th International Symposium on
Conference_Location :
New Orleans, LA
ISSN :
1530-0897
Print_ISBN :
978-1-4673-0827-4
Electronic_ISBN :
1530-0897
Type :
conf
DOI :
10.1109/HPCA.2012.6168940
Filename :
6168940
Link To Document :
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