A background interstage gain calibration for a 16-bit pipelined ADC

Pipelined analog-to-digital converters (ADCs) are sensitive to distortion introduced by the residue amplifiers in their first few stages. This paper presents a background self-calibration technique that can correct linear errors in the interstage amplifier of pipeline ADCs. Pseudo-random sequence and stage redundancy in pipelined architecture are used to measure opamp gain errors. With this calibration architecture used in a 16-bit 160 MHz pipelined ADC, the simulation results show that a signal-to-noise-and-distortion performance improves from 59.8126 dB to 75.1042 dB, and a spurious-free dynamic range performance from 83.97 dB to 97.8319 dB.