DocumentCode
3539926
Title
On generating compact test sequences for synchronous sequential circuits
Author
Pomeranz, Irith ; Reddy, Sudhakar M.
Author_Institution
Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
fYear
1995
fDate
18-22 Sep 1995
Firstpage
105
Lastpage
110
Abstract
We present a procedure to generate short test sequences for synchronous sequential circuits described at the gate level. Short test sequences are important in reducing test application time and memory requirements. The proposed procedure constructs a test sequence using a combination of fault-independent and fault-oriented criteria. Experimental results are presented to demonstrate its effectiveness
Keywords
logic CAD; logic design; logic testing; sequential circuits; compact test sequences; fault-independent criteria; fault-oriented criteria; memory requirements; synchronous sequential circuits; test application time; Application software; Circuit faults; Circuit testing; Cities and towns; Combinational circuits; Electrical fault detection; Fault detection; Sequential analysis; Sequential circuits; Synchronous generators;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 1995, with EURO-VHDL, Proceedings EURO-DAC '95., European
Conference_Location
Brighton
Print_ISBN
0-8186-7156-4
Type
conf
DOI
10.1109/EURDAC.1995.527394
Filename
527394
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