DocumentCode :
3540106
Title :
Parabix: Boosting the efficiency of text processing on commodity processors
Author :
Lin, Dan ; Medforth, Nigel ; Herdy, Kenneth S. ; Shriraman, Arrvindh ; Cameron, Rob
Author_Institution :
Sch. of Comput. Sci., Simon Fraser Univ., Burnaby, BC, Canada
fYear :
2012
fDate :
25-29 Feb. 2012
Firstpage :
1
Lastpage :
12
Abstract :
Modern applications employ text files widely for providing data storage in a readable format for applications ranging from database systems to mobile phones. Traditional text processing tools are built around a byte-at-a-time sequential processing model that introduces significant branch and cache miss penalties. Recent work has explored an alternative, transposed representation of text, Parabix (Parallel Bit Streams), to accelerate scanning and parsing using SIMD facilities. This paper advocates and develops Parabix as a general framework and toolkit, describing the software toolchain and run-time support that allows applications to exploit modern SIMD instructions for high performance text processing. The goal is to generalize the techniques to ensure that they apply across a wide variety of applications and architectures. The toolchain enables the application developer to write constructs assuming unbounded character streams and Parabix´s code translator generates code based on machine specifics (e.g., SIMD register widths). The general argument in support of Parabix technology is made by a detailed performance and energy study of XML parsing across a range of processor architectures. Parabix exploits intra-core SIMD hardware and demonstrates 2×-7× speedup and 4× improvement in energy efficiency when compared with two widely used conventional software parsers, Expat and Apache-Xerces. SIMD implementations across three generations of x86 processors are studied including the new SandyBridge. The 256-bit AVX technology in Intel SandyBridge is compared with the well established 128-bit SSE technology to analyze the benefits and challenges of 3-operand instruction formats and wider SIMD hardware. Finally, the XML program is partitioned into pipeline stages to demonstrate that thread-level parallelism enables the application to exploit SIMD units scattered across the different cores, achieving improved performance (2× on 4 cores) while- maintaining single-threaded energy levels.
Keywords :
XML; parallel processing; text analysis; 3-operand instruction formats; AVX technology; Apache-Xerces; Expat; Intel SandyBridge; Parabix code translator; SIMD facilities; SSE technology; XML parsing; branch miss penalties; byte-at-a-time sequential processing model; character streams; commodity processors; data storage; efficiency boosting; intracore SIMD hardware; parallel bit streams; pipeline stages; single-threaded energy levels; software toolchain; text files; text processing tools; thread-level parallelism; x86 processors; Computer architecture; Energy efficiency; Hardware; Program processors; Registers; Text processing; XML;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
High Performance Computer Architecture (HPCA), 2012 IEEE 18th International Symposium on
Conference_Location :
New Orleans, LA
ISSN :
1530-0897
Print_ISBN :
978-1-4673-0827-4
Electronic_ISBN :
1530-0897
Type :
conf
DOI :
10.1109/HPCA.2012.6169041
Filename :
6169041
Link To Document :
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