• DocumentCode
    3540141
  • Title

    QuickIA: Exploring heterogeneous architectures on real prototypes

  • Author

    Chitlur, Nagabhushan ; Srinivasa, Ganapati ; Hahn, Scott ; Gupta, P.K. ; Reddy, Dheeraj ; Koufaty, David ; Brett, Paul ; Prabhakaran, Abirami ; Zhao, Li ; Ijih, Nelson ; Subhaschandra, Suchit ; Grover, Sabina ; Jiang, Xiaowei ; Iyer, Ravi

  • fYear
    2012
  • fDate
    25-29 Feb. 2012
  • Firstpage
    1
  • Lastpage
    8
  • Abstract
    Over the last decade, homogeneous multi-core processors emerged and became the de-facto approach for offering high parallelism, high performance and scalability for a wide range of platforms. We are now at an interesting juncture where several critical factors (smaller form factor devices, power challenges, need for specialization, etc) are guiding architects to consider heterogeneous chips and platforms for the next decade and beyond. Exploring heterogeneous architectures is challenging since it involves re-evaluating architecture options, OS implications and application development. In this paper, we describe these research challenges and then introduce a heterogeneous prototype platform called QuickIA that enables rapid exploration of heterogeneous architectures employing multiple generations of Intel processors for evaluating the implications of asymmetry and FPGAs to experiment with specialized processors or accelerators. We also show example case studies using the QuickIA research prototype to highlight its value in conducting heterogeneous architecture, OS and applications research.
  • Keywords
    computer architecture; field programmable gate arrays; multiprocessing systems; FPGA; Intel processors; OS implications; QuickIA research prototype; application development; architecture option re-evaluation; de-facto approach; field programmable gate arrays; heterogeneous architectures; heterogeneous chips; heterogeneous prototype platform; homogeneous multicore processors; specialized accelerators; specialized processors; Computer architecture; Field programmable gate arrays; Hardware; Linux; Prototypes; Quality of service; Sockets;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High Performance Computer Architecture (HPCA), 2012 IEEE 18th International Symposium on
  • Conference_Location
    New Orleans, LA
  • ISSN
    1530-0897
  • Print_ISBN
    978-1-4673-0827-4
  • Electronic_ISBN
    1530-0897
  • Type

    conf

  • DOI
    10.1109/HPCA.2012.6169046
  • Filename
    6169046