Timing influenced force directed floorplanning

Author

Youssef, Habib ; Sait, Sadiq M. ; Al-Farra, Khalid J.

Author_Institution

Dept. of Comput. Eng., King Fahd Univ. of Pet. & Miner., Dhahran, Saudi Arabia

fYear

1995

fDate

18-22 Sep 1995

Firstpage

156

Lastpage

161

Abstract

We present a timing driven floorplanning program for general cell layouts. The approach used combines quality of force directed approach with that of constraint graph approach. A floorplan solution is produced in two steps. First a timing and connectivity driven topological arrangement is obtained using a force directed approach. In the second step, the topological arrangement is transformed into a legal floorplan. The objective of the second step is to minimize the overall area of the floorplan. The floorplanner is validated with circuits of sizes varying from 7 to 125 blocks

Keywords

CMOS integrated circuits; circuit layout CAD; circuit optimisation; integrated circuit layout; network topology; timing; α-critical paths; SCMOS technology; VLSI layout; connectivity driven topological arrangement; constraint graph approach; directed acyclic graphs; floorplan optimization; general cell layouts; timing influenced force directed floorplanning; Circuit optimization; DH-HEMTs; Design methodology; Electronic mail; Law; Legal factors; Minerals; Petroleum; Shape; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 1995, with EURO-VHDL, Proceedings EURO-DAC '95., European

Conference_Location

Brighton

Print_ISBN

0-8186-7156-4

Type

conf

DOI

10.1109/EURDAC.1995.527402

Filename

527402