Improvements to circuit diagnosis through hierarchical modelling

The testing of large scale analogue integrated circuits has become increasingly significant with the advent of mixed signal ASICs, of which circuit size and complexity are ever increasing. The domain for analogue circuit testing is at present lagging behind its digital counterpart on which a lot of development has been done, leading to a very mature technology and many comprehensive software tools. Over the years, many different approaches have been proposed to tackle the complex issue of analogue testing. Amongst them is a powerful approach introduced by Wey (1987). This employs a Self Test (ST) Algorithm formulated on the Component Connection Model (CCM). We have improved on the approach of Wey in proposing an Optimal Tree Generation (OTG) Algorithm in conjunction with a novel Test Point Selection Procedure to select a set of test points to diagnose a given maximum number of possible faults. In this paper the authors propose two addition enhancements in the diagnosis procedure to compensate for the insufficiencies of their earlier works. These enhancements are namely, the partition generation algorithm and the backtracking of test results. The modifications needed for the adoption of a hierarchical approach into the diagnosis procedure are also discussed, These are the imposing of a hierarchical partition rule for tester/testee partition in every test cycle and the re-interpretation of the decision algorithms at the circuit graph level to consider the effect of hierarchical graph edges