Title :
Limits to performance spread tuning using adaptive voltage and body biasing
Author :
Meijer, Maurice ; Pessolano, Francesco ; De Gyvez, José Pineda
Author_Institution :
Philips Res. Labs., Eindhoven, Netherlands
Abstract :
We examine technology constraints on tuning active power and delay using adaptive voltage scaling (AVS) and adaptive body biasing (ABB) design techniques. To serve this purpose, a test circuit was fabricated in a 90 nm triple-well low-power CMOS technology. The presented analysis is based on a ring oscillator running at 488 MHz and a circular shift register with 8 K flip-flops and 50 K gates. Measurement results indicate that it is possible to reach 24.4× power savings by 6.1× frequency downscaling using AVS, ±24% power and ±22% frequency tuning at nominal conditions using ABB only, 127× power savings with 37.4× frequency downscaling by combining AVS and ABB.
Keywords :
CMOS analogue integrated circuits; CMOS digital integrated circuits; UHF oscillators; circuit tuning; delays; flip-flops; logic gates; low-power electronics; network analysis; shift registers; 488 MHz; 90 nm; active power tuning; adaptive body biasing; adaptive voltage scaling; circular shift register; delay tuning; design techniques; flip-flops; frequency downscaling; frequency tuning; gates; low-power designs; performance spread tuning; power savings; ring oscillator; triple-well low-power CMOS technology; CMOS technology; Circuit optimization; Circuit testing; Delay; Flip-flops; Frequency; Ring oscillators; Shift registers; Tuning; Voltage;
Conference_Titel :
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN :
0-7803-8834-8
DOI :
10.1109/ISCAS.2005.1464510
