Title :
Scalable performance scheduling for hardware-software cosynthesis
Author :
Benner, Th. ; Ernst, R. ; Österling, A.
Author_Institution :
Inst. fur Datenverarbeitungsanlagen, Braunschweig, Germany
Abstract :
The paper presents a static process scheduling approach as a front-end to hardware-software cosynthesis of small embedded systems which allows global system optimization. Unlike earlier approaches, scheduling is executed before hardware definition assuming scalable system performance. Scheduling supports process communication and external timing requirements. We explain the algorithm and give results using an example
Keywords :
computer aided software engineering; high level synthesis; logic design; processor scheduling; real-time systems; resource allocation; external timing requirements; global system optimization; hardware-software cosynthesis; process communication; scalable performance scheduling; scalable system performance; small embedded systems; static process scheduling approach; Automation; Computer architecture; Coprocessors; Embedded system; Hardware; Logic; Partitioning algorithms; Scheduling algorithm; System performance; Timing;
Conference_Titel :
Design Automation Conference, 1995, with EURO-VHDL, Proceedings EURO-DAC '95., European
Conference_Location :
Brighton
Print_ISBN :
0-8186-7156-4
DOI :
10.1109/EURDAC.1995.527403
