Device technology for body biasing scheme

Author

Imai, Kiyotaka ; Yamagata, Yasushi ; Masuoka, Sadaaki ; Kimuzuka, Naohiko ; Yasuda, Yuri ; Togo, Mitsuhiro ; Ikeda, Masahiro ; Nakashiba, Yasutaka

Author_Institution

Adv. Device Dev. Div., NEC Electron. Corp., Kanagawa, Japan

fYear

2005

fDate

23-26 May 2005

Firstpage

13

Abstract

We report power-aware 65-nm node CMOS device technology suitable for a body biasing scheme. For high-performance CMOS, both channel and halo profiles have been optimized to enhance the body-bias effect of 45-nm gate length devices. Standby leakage reduction without device reliability compromise has been demonstrated with simultaneous voltage control of the body bias and power supply. Moreover, high-k gate dielectric "HfSiON" has been adopted to reduce both gate leakage and GIDL, which are the dominant standby leakage components of low standby power CMOS.

Keywords

CMOS integrated circuits; electric potential; hafnium compounds; integrated circuit reliability; leakage currents; optimisation; power control; silicon compounds; voltage control; 45 nm; 65 nm; GIDL; HfSiON; body bias control; body biasing scheme; channel profile optimization; device reliability; device technology; gate leakage; halo profile; high-k gate dielectric; power supply control; power-aware CMOS device technology optimization; standby leakage reduction; CMOS technology; Emergency power supplies; Gate leakage; Inverters; Leakage current; National electric code; Power dissipation; Subthreshold current; Threshold voltage; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on

Print_ISBN

0-7803-8834-8

Type

conf

DOI

10.1109/ISCAS.2005.1464512

Filename

1464512