A systematic framework for high throughput MAP decoder VLSI architectures

Author

Elassal, Mahmoud ; Kumar, Ashok ; Bayoumi, Magdy

Author_Institution

Center for Adv. Comput. Studies, Univ. of Louisiana, Lafayette, LA, USA

fYear

2005

fDate

23-26 May 2005

Firstpage

29

Abstract

The paper presents a systematic method for the development of high throughput MAP decoder architectures. High throughput is achieved by exploiting more algorithmic parallelism. The paper proposes the use of the trellis-time graph to study the parallel MAP decoder architectures analytically. A parameterized windowing approach is developed to construct the trellis-time graph of the decoding operation. Next, an exhaustive search is used to explore the parallelism vs. hardware resources systematically. This method is applied towards the design of a MAP decoder that has a frame of size 320 bits. A tradeoff among the decoding delay, number of kernels, number of BMM banks, and number of SMM banks is presented.

Keywords

VLSI; delays; graph theory; maximum likelihood decoding; network analysis; parallel algorithms; parallel architectures; search problems; MAP decoder architectures; algorithmic parallelism; branch metric memory banks; decoding delay; hardware resources; high throughput MAP decoder VLSI architectures; kernels; parallel MAP decoder architectures; parallel architectures; parameterized windowing approach; state metric memory banks; trellis-time graph; Approximation algorithms; Computational complexity; Computer architecture; Hardware; Iterative algorithms; Iterative decoding; Kernel; Parallel processing; Throughput; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on

Print_ISBN

0-7803-8834-8

Type

conf

DOI

10.1109/ISCAS.2005.1464516

Filename

1464516