Design and FPGA Implementation of MAC-PHY Interface Based on PCI Express for Next-Generation WLANs

In this paper, the design and implementation of a novel MAC-PHY interface (MPI) protocol are presented, based on peripheral component interconnect express (PCIe) bus and field programmable gate array (FPGA). Through the high-performance FPGA and high-speed bus PCIe, the proposed MPI architecture realizes a transparent, reliable, high-rate, low-delay, and efficient communication between medium access control (MAC) layer and physical (PHY) layer. By undertaking certain functions of the central processing unit (CPU) for MAC layer and FPGAs for PHY layer, MPI can reduce the burden of them. Thus they have more resources for processing mass data and complex algorithms, which will help systems achieve gigabit-per-second (Gbps) throughput demanded in the next generation wireless local area networks (WLANs). Based on a very high throughput (VHT) WLAN testbed system, the MPI protocol is implemented on Xilinx Virtex-6 LX130T FPGA. Test results under indoor environments verify that the proposed MPI architecture can achieve a throughput of 1.21Gbps.