Zero skew clock routing with tree topology construction using simulated annealing method

In synchronous VLSI designs, clock network quality plays a key role in determining system performance. As a part of clock routing, the clock tree topology generation is a crucial problem to the solution. We explore the topology characteristics of clock trees and give a simulated annealing method solving the clock routing problem by manipulating the clock tree topology. The elaborately designed rules of generating a neighbor solution at each iteration step of the simulated annealing process have an important impact on the final solution. As the experimental results illustrated, our approach is effective for zero skew clock routing compared with algorithms which have a topology generation method using top-down and bottom-up heuristics, respectively.