DocumentCode
3540860
Title
High-efficiency control structure for CMOS flash memory charge pumps
Author
Boffino, C. ; Cabrini, A. ; Khouri, O. ; Torelli, G.
Author_Institution
Dept. of Electron., Pavia Univ., Italy
fYear
2005
fDate
23-26 May 2005
Firstpage
121
Abstract
A basic drawback of charge pump circuits is represented by undesired power losses, that must be reduced as much as possible in particular for portable applications. This paper presents a control structure conceived to reduce the power consumption of voltage elevators based on Dickson topology. To evaluate the effectiveness of the proposed control scheme, a new definition of power efficiency is introduced. The presented solution provides an effective power management, thus ensuring an efficiency improvement of about 40% during stand-by.
Keywords
CMOS memory circuits; flash memories; network topology; power consumption; power supply circuits; voltage control; CMOS flash memory; Dickson topology; charge pump circuits; high-efficiency control structure; power efficiency; power management; reduced power consumption; voltage elevators; CMOS memory circuits; Capacitors; Charge pumps; Elevators; Flash memory; Power supplies; Regulators; Switches; Topology; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN
0-7803-8834-8
Type
conf
DOI
10.1109/ISCAS.2005.1464539
Filename
1464539
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