Design technique of an on-chip, high-voltage charge pump in SOI

Author

Hoque, M.R. ; Ahmad, T. ; McNutt, T. ; Mantooth, A. ; Mojarradi, M.M.

Author_Institution

Arkansas Univ., Fayetteville, AR, USA

fYear

2005

fDate

23-26 May 2005

Firstpage

133

Abstract

A design methodology for an on-chip charge pump that utilizes SOI CMOS charge transfer switches is presented. The limiting factors of a bulk CMOS process to produce a high-voltage, on-chip converter are outlined. The power efficiency has been improved due to low stray capacitance inherent in the SOI process. The circuit has been simplified from the conventional charge pump for implementation in an SOI process, which saves active chip area. A 9-stage charge pump is designed to produce a 27 V output from a 3.3 V supply. The design was fabricated in a 0.35 μm SOI CMOS process. A power efficiency of 91% is achieved at a load current of approximately 40 μA.

Keywords

CMOS integrated circuits; capacitance; power supply circuits; silicon-on-insulator; 0.35 micron; 27 V; 3.3 V; 91 percent; CMOS charge transfer switches; SOI; bulk CMOS process; high-voltage charge pump; on-chip charge pump; on-chip converter; power efficiency; stray capacitance; CMOS process; Charge pumps; Circuit topology; Degradation; Diodes; MOSFETs; Microelectromechanical devices; Switches; System-on-a-chip; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on

Print_ISBN

0-7803-8834-8

Type

conf

DOI

10.1109/ISCAS.2005.1464542

Filename

1464542