Vertical double-gate structure with nonvolatile charge storage node for 1T-DRAM cell device

In this paper, a novel vertical channel double-gate 1T-DRAM cell transistor with nonvolatile charge storage node was proposed. Excellent sensing margin and good retention characteristic have been achieved by programming charge in the storage node. Relatively long channel double-gate 1T-DRAM cell with fully depleted thin body on bulk Si wafer without increasing cell size could be achieved. It was found that the peak body doping on the drain side gives better retention characteristic. Proposed device is expected to be a very promising candidate for future 1T DRAM cell.