DocumentCode :
3540906
Title :
Program/erase model of NAND-type nitride-based charge trapping flash memories
Author :
Kim, Doo-Hyun ; Park, Byung-Gook
Author_Institution :
Inter-Univ. Semicond. Res. Center, Seoul Nat. Univ., Seoul, South Korea
fYear :
2008
fDate :
15-16 June 2008
Firstpage :
1
Lastpage :
3
Abstract :
In this paper, the authors developed the P/E model of NAND-type nitride-based charge trapping flash memories with transient ONO field, tunneling currents, trapped charge density and threshold voltage shift. The simulated results show acceptable V¿ shift operation of SONOS NAND flash memory using FN and direct tunneling in P/E process. This modeling works account for the V¿ shift as a function of applied gate voltage, time, and thickness of silicon oxide and silicon nitride layers and can be used for optimizing the ONO geometry and parameters for maximum performance.
Keywords :
NAND circuits; circuit optimisation; flash memories; silicon compounds; NAND-type nitride-based charge trapping flash memories; ONO geometry; SONOS NAND flash memory; SiN; SiO2; applied gate voltage; optimization; program-erase model; silicon nitride layers; silicon oxide thickness; threshold voltage shift; transient ONO field; trapped charge density; tunneling currents; Charge carrier processes; Current density; Dielectric constant; Dielectric substrates; Electron traps; Electronic mail; Equations; Flash memory; SONOS devices; Tunneling;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Silicon Nanoelectronics Workshop, 2008. SNW 2008. IEEE
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4244-2071-1
Type :
conf
DOI :
10.1109/SNW.2008.5418385
Filename :
5418385
Link To Document :
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