4-bit/cell charge trapping flash device for high density formed in recess region

Localized charge trapping device based on SONOS flash structures has been considered as a very promising candidate for future NVM beyond the floating gate technology, due to its various advantages. Recently, various device structures have been proposed to overcome the scaling limits of the conventional SONOS memories. Especially, the capability of 2-bit/cell operation from the physically separated storage node is very attractive for ultra-high density memory application. The spacer-type and split-gate structure could be possible physical isolation of bits, but were not scalable to sub-80 ran due to the difficulties in geometry controllability and performance degradation. To shrink gate length down to sub-100 nm and remove the interference between storage nodes by charge redistribution, we have proposed compact 2-bit/cell SONOS device with recessed channel structure. In this paper, we propose an advanced cell concept for 4-bit/cell (or 2-Tr/cell) SONOS memory. We focus on how to increase V¿ margin for bits near the bottom corner of the recessed region, and also show reasonable isolation between adjacent cells.