SRAM yield and performance enhancements with tri-gate bulk MOSFETs

Multi-gate devices are expected to enable continued scaling beyond the 32nm node in part due to their improved gate control of the channel versus planar MOSFETs. Static random access memory (SRAM) scaling, which requires increasing design margins despite decreasing layout area, may motivate the transition to a multi-gate architecture. Tri-gate bulk devices are an attractive multi-gate option because of their high compatibility with existing circuit designs and processes. In this work. SRAM cell simulations are used to quantify the expected yield improvements and design tradeoffs with tri-gate devices. We show that up to two standard deviations (sigma) of yield enhancement can be expected for both read and write margins, without penalty to cell area or access time. The tri-gate SRAM cell can be further optimized to simultaneously reduce cell area and minimum operating voltage, V_min.