Title :
On the potentiality of planar independent double gate for capacitorless eDRAM
Author :
PUGET, Sophie ; BOSSU, Germain ; MAZOYER, Pascale ; Portal, Jean-Michel ; Masson, Pascal ; BOUCHAKOUR, Rachid ; Skotnicki, Thomas
Author_Institution :
STMicroelectronics, Crolles, France
Abstract :
Thin film devices are potential candidates for the 32 nm technology node and beyond. In this perspective, thin film architecture as embedded capacitorless eDRAM remains to be assessed. Planar Independent Double Gate architecture is considered here. The analysis of technological parameters and their scaling are evaluated on memory effect. Optimal gate stack for IDG appears to be metal /poly P+ combination for this architecture.
Keywords :
DRAM chips; thin film devices; capacitorless eDRAM; memory effect; planar independent double gate; size 32 nm; thin film architecture; thin film devices; Analytical models; Application specific integrated circuits; CMOS technology; Doping; Potential well; Random access memory; Semiconductor films; Silicon; Thin film devices; Transistors;
Conference_Titel :
Silicon Nanoelectronics Workshop, 2008. SNW 2008. IEEE
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4244-2071-1
DOI :
10.1109/SNW.2008.5418395
