Improving the cell characteristics using arch-active profile in NAND flash memory having 60.nm design rule

Author

Kang, Daewoong ; Chang, Sungnam ; Lee, Jung Hoon ; Park, Han, II ; Seo, Seunggun ; Kwon, Gideok ; Bae, Kyungmi ; Kim, Inyoung ; Lee, Eunjung ; Choi, Jeong-Hyuk ; Park, Byung- Gook ; Lee, Jong Duk ; Shin, Hyungcheol

Author_Institution

Inter-Univ. Semicond. Res. Center & Sch. of Electr. Eng., Seoul Nat. Univ., Seoul, South Korea

fYear

2008

fDate

15-16 June 2008

Firstpage

1

Lastpage

2

Abstract

Recently the cell integration density of NAND flash memory is increasing rapidly due to its simple structure suitable for high resolution lithography. Therefore, the reduction of cell size has been the most important issue. However, with the increase in the number of the cells and the scale-down of the cell size, the NAND cell string has some problems such as small on-cell current and poor program/erase speed [1-2] but also the current fluctuation due to RTS noise. In this work, in order to overcome some problems, we would like to propose the active profile having arch structure in NAND flash having floating gate. Also, we applied arch structure on poly-Si/WaÂ¿ stack gate of 60 nm design-rule NAND flash device for the first time, which improved the cell operation characteristics such cell current, program/erase speed and Id fluctuation of RTS noise.

Keywords

NAND circuits; flash memories; lithography; network synthesis; NAND cell string; NAND flash memory; arch-active profile; cell integration density; design rule; high resolution lithography; Flash memory; Fluctuations; Lithography; Noise measurement; Nonvolatile memory; Oxidation; Semiconductor device noise; Silicon compounds; Voltage; Wet etching;

fLanguage

English

Publisher

ieee

Conference_Titel

Silicon Nanoelectronics Workshop, 2008. SNW 2008. IEEE

Conference_Location

Honolulu, HI

Print_ISBN

978-1-4244-2071-1

Type

conf

DOI

10.1109/SNW.2008.5418397

Filename

5418397