Improving the cell characteristics using arch-active profile in NAND flash memory having 60.nm design rule

Recently the cell integration density of NAND flash memory is increasing rapidly due to its simple structure suitable for high resolution lithography. Therefore, the reduction of cell size has been the most important issue. However, with the increase in the number of the cells and the scale-down of the cell size, the NAND cell string has some problems such as small on-cell current and poor program/erase speed [1-2] but also the current fluctuation due to RTS noise. In this work, in order to overcome some problems, we would like to propose the active profile having arch structure in NAND flash having floating gate. Also, we applied arch structure on poly-Si/Wa¿ stack gate of 60 nm design-rule NAND flash device for the first time, which improved the cell operation characteristics such cell current, program/erase speed and Id fluctuation of RTS noise.