FPGA Implementation of Full Parallel and Pipelined FFT

This paper addresses the real-time demand of radix-4 FFT processor in modern digital signal processing domain. Full parallel and pipelined architecture can be a good solution while too much hardware is consumed. Therefore a useful optimization method of complex multiplier and twiddle factor which has been successfully used to implement the FFT algorithms achieving a reduction in multipliers´ usage of up to 38 percent. Furthermore, we also present a useful truncation metric about fixed-point calculation.