• DocumentCode
    3541248
  • Title

    Design optimization of NEMS switches for single-electron logic applications

  • Author

    Pruvost, Benjamin ; Mizuta, Hiroshi ; Oda, Shunri

  • Author_Institution
    QNERC, Tokyo Inst. of Technol., Tokyo, Japan
  • fYear
    2008
  • fDate
    15-16 June 2008
  • Firstpage
    1
  • Lastpage
    2
  • Abstract
    In this work, we focus on the design optimization and the analysis of the latter device in order to evaluate its merit and demerit. We propose a realistic low-voltage window design methodology, which could actually also be used for systematical design of conventional NEMS switches. We also demonstrate some applications that arise from the movable gate, such as a way to cope with the random background charge problem and to build logic functions.
  • Keywords
    logic devices; nanoelectromechanical devices; optimisation; single electron devices; switches; NEMS switches; design optimization; logic functions; low-voltage window design; single-electron logic applications; Capacitance; Capacitors; Design optimization; Electrodes; Logic design; Logic devices; Nanoelectromechanical systems; Quantum mechanics; Switches; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Silicon Nanoelectronics Workshop, 2008. SNW 2008. IEEE
  • Conference_Location
    Honolulu, HI
  • Print_ISBN
    978-1-4244-2071-1
  • Type

    conf

  • DOI
    10.1109/SNW.2008.5418425
  • Filename
    5418425