Si based single-electron transistor with ultra-thin oxide tunnel barriers fabricated using controlled CMP

Si single-electron transistors exhibiting room temperature operation have been reported in the literature and have also been shown to have excellent long-term charge stability as compared to metal tunnel junction devices. However, these devices suffer from a number of problems that will preclude their use in any practical application. These problems are due to uncontrolled dot size and tunnel barrier thickness. In this paper we present the result derived from the characterization of the different fabrication steps and the device. We have developed a different method to fabricate Si-SET using lithography, dry etching, and chemical mechanical polishing. Our method produces an SET with well-defined geometry of the dot and most importantly a high quality, well-controlled tunnel oxide.