Fabrication and improved characteristics of self-aligned dual-gate single-electron transistors

Single-electron transistors (SETs) have been expected to become one of the promising devices in future ultra-low power and high-density systems. Especially, silicon based SETs have advantages in the fabrication and design of SET and MOSFET hybrid circuits. Due to its potential, lots of research has been conducted and various structures have been introduced. However, low operation temperature and poor fabrication controllability still remain as main obstacles to widespread utilization. In this respect, dualgate SETs using electrical tunneling barriers have strengths compared to other structures. This is because the height of the tunneling barriers can be controlled through external bias and the quantum dot size is further decreased due to electric field effects. In our research, dual-gate SETs were fabricated with a CMOS compatible and self-aligned process. Process parameters were optimized in order to reduce the total capacitance of a quantum dot, and Coulomb oscillation peak was observed in the roomtemperature operation of the fabricated device.