Comparison of the horizontal and the vertical common subexpression elimination methods for realizing digital filters

Common subexpression elimination (CSE) techniques address the issue of minimizing the number of adders needed to implement the coefficient multipliers in digital filters. Two classes of common subexpressions (CS) occur in the canonic signed digit (CSD) representation of coefficients, called the horizontal and the vertical CS. Previous works have not addressed the trade-offs in using these two types of CS on the delay and the number of multiplier block adders. We provide a comparison of hardware reductions achieved using the horizontal and the vertical CS in realizing digital filters. We show that the CSE technique employing horizontal CS offers better reductions in the number of adders and critical paths than its vertical CS counterpart in practical linear phase finite impulse response (LPFIR) filter implementations. Our simulation results show that the hardware reductions offered by the vertical CS in implementing infinite impulse response (IIR) filters are improved compared to their LPFIR counterparts.