Title :
Integration of VHDL into a system design environment
Author :
Schwoerer, Ludwig ; Lück, Matthias ; Schröder, Hartmut
Author_Institution :
Dortmund Univ., Germany
Abstract :
Verification of image processing systems is mainly done on the basis of image sequence simulations. To achieve high simulation efficiency, our compiled code simulator MSIPC offers a high performance clock period precision simulation, according to the SDF simulation paradigm. Furthermore it supports mixed mode (e.g. VHDL) simulations via coupling to external simulators, and via cross-compiling
Keywords :
formal verification; hardware description languages; image processing equipment; image sequences; logic CAD; logic design; MSIPC; SDF simulation paradigm; VHDL; compiled code simulator; cross-compiling; high performance clock period precision simulation; image processing systems; system design environment; verification; Algorithm design and analysis; Application specific integrated circuits; Circuit simulation; Clocks; Computational modeling; Hardware; Image processing; Image sequences; Signal processing algorithms; System testing;
Conference_Titel :
Design Automation Conference, 1995, with EURO-VHDL, Proceedings EURO-DAC '95., European
Conference_Location :
Brighton
Print_ISBN :
0-8186-7156-4
DOI :
10.1109/EURDAC.1995.527416
