Managing substrate and interconnect noise from high performance repeater insertion in a mixed-signal environment

With technology advancements in the very-deep submicrometer (VDSM) regime and system-on-chip (SOC) integration, high performance, low-voltage, and low-noise are becoming stringent challenges. Interconnect and crosstalk dominated digital design requires solutions to manage interconnect delay and crosstalk noise. SOC integration requires minimal interaction between the digital and analog/RF on-chip blocks that operate at increasingly lower power supplies. Such power supplies affect the signal-to-noise ratio of both the analog/RF as well as the digital blocks. These topics describe the general area of the paper. High-performance digital buffers targeting SOC are presented. Methods for reducing the impact of interconnect and substrate crosstalk generated by the buffers with implications on the on-chip analog/RF and digital blocks are discussed.