DocumentCode
3541822
Title
A new design method to modulo 2n-1 squaring
Author
Cao, Bin ; Srikanthan, Thambipillai ; Chang, Chip-Hong
Author_Institution
Centre for High Performance Embedded Syst., Nanyang Technol. Univ., Singapore, Singapore
fYear
2005
fDate
23-26 May 2005
Firstpage
664
Abstract
The paper presents a novel method for modulo 2n-1 squaring using the exponent reduction property of powers of 2 modulo 2n-1. An exponent triangle is created to simplify the design approach. In contrast to methods based on the periodic properties of powers of 2 modulo 2n-1, our graph based design method is appealing and yields a solution with direct correspondence to the modulo squaring structure. Simulation results show that the carry saver adder (CSA) tree for the proposed method lowers the hardware cost by more than half of that generated by the multiplier-based method. The overall delay has also been reduced by two levels of the CSA tree in general.
Keywords
delays; digital arithmetic; graph theory; integrated circuit design; carry saver adder tree; exponent reduction property; exponent triangle; graph based design method; modular multiplication; modular squaring; modulo squaring; multiplier-based method; periodic properties; Adders; Costs; Design methodology; Digital signal processing; Embedded system; Hardware; Paper technology; Periodic structures; Table lookup; Tree graphs;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN
0-7803-8834-8
Type
conf
DOI
10.1109/ISCAS.2005.1464675
Filename
1464675
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