High-level synthesis under I/O timing and memory constraints

In the design of complex systems-on-chips, it is necessary to take into account communication and memory access constraints for the integration of a dedicated hardware accelerator. We present a methodology and a tool that allow the high-level synthesis of a DSP algorithm, under both I/O timing and memory constraints. Based on formal models and a generic architecture, this tool helps the designer to find a reasonable trade-off between the required I/O timing behavior and the internal memory access parallelism of the circuit. The interest of our approach is demonstrated by the case study of an FFT algorithm.