A synthesis scheme for simultaneous scheduling, binding, partitioning and placement with resources operating at multiple voltages

One promising technique to reduce power consumption is to power a chip with multiple supply voltages. However, as noticed by M.C. Johnson and K. Roy (see ACM Trans. Design Auto. Electronic Syst., vol.2, p.227-48, 1997), multiple voltage designs can cause a number of serious layout problems. We have shown that the layout problems can be partially solved by the addition of a partitioning step into the synthesis flow. A more subtle solution to solve the layout problems requires placement also to be included in the design flow. We present a synthesis scheme, following a simulated annealing engine, to minimize power consumption and area with resources operating at multiple voltages under timing constraints. The scheme simultaneously considers many correlated factors, such as scheduling, binding, partitioning and placement, to reduce power consumption due to both functional units and interconnections between and among them. Experiments with a number of DSP benchmarks show that the proposed algorithm can achieve significant reduction in power and area.