DocumentCode
3541920
Title
Planar inductors with interleaved conductors for integrated power applications
Author
Salles, Alain ; Estibals, Bruno ; Bourrier, David ; Alonso, Corinne
Author_Institution
Lab. d´´Autom. et d´´Anal. des Syst., CNRS, Toulouse, France
fYear
2005
fDate
23-26 May 2005
Firstpage
724
Abstract
This paper presents a new topology of inductor allowing a decreasing of the conductor serial resistance. After validating the concept of conductors interleaving, technological process flow and results are presented.
Keywords
electric resistance; electron device testing; integrated circuit technology; network topology; power supply circuits; system-on-chip; thick film inductors; conductor serial resistance; inductor topology; integrated power applications; interleaved conductors; interleaving concept; planar inductors; portable applications; systems on chip; technological process flow; Circuit topology; Conductors; Couplings; Electric resistance; Inductance; Inductors; Interleaved codes; Sensor systems and applications; Space technology; System-on-a-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Print_ISBN
0-7803-8834-8
Type
conf
DOI
10.1109/ISCAS.2005.1464690
Filename
1464690
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