• DocumentCode
    3542037
  • Title

    Pipeline ADC linearity testing with dramatically reduced data capture time

  • Author

    Yu, Zhongjun ; Chen, Degang ; Geiger, Randy ; Papantonopoulos, Yiannis

  • Author_Institution
    Iowa State Univ., Ames, IA, USA
  • fYear
    2005
  • fDate
    23-26 May 2005
  • Firstpage
    792
  • Abstract
    A system identification based method for testing pipeline ADC linearity is presented. In the method, the pipeline ADC is described by an identifier model consisting of a set of nonlinear equations parameterized with some unknown parameters. A small number of input output response data points of the ADC is then used to identify those unknown parameters. The identified model is then used to compute the ADC´s full-code linearity information. Comparing to standard histogram based full-code linearity test methods, the proposed method can reduce the data capture time by a factor of 100 to 1000 without appreciably degrading the testing accuracy. Both simulation results and experimental results are included which demonstrate the efficacy of the proposed method.
  • Keywords
    analogue-digital conversion; identification; integrated circuit testing; nonlinear equations; pipeline processing; ADC full-code linearity information; ADC input output response data points; data capture time; identifier model; parameterized nonlinear equations; pipeline ADC linearity testing; simulation; standard histogram based full-code linearity test methods; system identification based method; testing accuracy; Circuit testing; Degradation; Histograms; Instruments; Linearity; Nonlinear equations; Pipelines; System identification; System testing; Tail;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
  • Print_ISBN
    0-7803-8834-8
  • Type

    conf

  • DOI
    10.1109/ISCAS.2005.1464707
  • Filename
    1464707