A 12.5 Gbps CMOS input sampler for serial link receiver front end

This paper presents a high-speed CMOS input sampler used for a serial link receiver front end. The input sampler consists of a comparator, a SR latch and a D flip-flop. Because a parallel architecture is used for the 1:8 demultiplexing and 3× oversampling is utilized for data recovery, there are 24 input samplers in the receiver front end. These input samplers are implemented in a TSMC 0.18 μm 1P6M process with area of 252*162 μm². The circuits can operate at maximum input data rate of 12.7 Gbit/s with differential signal of 300 mV using a supply voltage of 1.8V.