Dependence of Differential flip-flops performance on clock slope and relaxation of clock network design

In this paper, the impact of the clock slope on the performance of high-speed Differential flip-flops in a 65-nm CMOS technology is discussed. Usually the local network that distributes the clock signal to the flip-flops is designed to guarantee a steep clock waveform in order to not compromise the flip-flops performance. We show that, even doubling the clock slope (or more) with respect to typical F02 ÷ F03 values, the impact on the Differential flip-flops speed is negligible. Correspondently, their energy dissipation increases but this drawback is balanced by the lower consumption resulting from the local clock distribution buffers, whose size/number can be reduced. Therefore, a tradeoff arises and, on the whole, the optimum clock slope can be different from the usual F02 ÷ F03 assumption. This result allows to relax the local (domain) clock network design, thereby reducing the energy consumption associated with the distribution of the clock within a domain. Results with a 65-nm technology show that the resulting energy saving can be up to 60%.