DocumentCode
3542616
Title
DCM demapper for MB-OFDM on FPGA
Author
Véstias, Mário ; Santos, Hugo ; Sarmento, Helena
fYear
2010
fDate
9-13 Jan. 2010
Firstpage
125
Lastpage
126
Abstract
This paper presents the implementation of a dual carrier modulation (DCM) demapper, proposed as part of a MB-OFDM UWB receiver to be integrated in an FPGA. The implemented DCM demapper, together with the FFT and the Viterbi decoder, were implemented in a Xilinx Virtex-5 FPGA. The complete system was modelled and tested with Matlab/Simulink and the part implemented in FPGA was connected to Matlab using the System Generator from Xilinx.
Keywords
OFDM modulation; fast Fourier transforms; field programmable gate arrays; radio receivers; DCM demapper; FFT; FPGA; MB-OFDM; OFDM receiver; UWB receiver; Viterbi decoder; Xilinx Virtex-5; dual carrier modulation demapper; Decoding; Equations; Field programmable gate arrays; Frequency diversity; Hardware; Mathematical model; OFDM modulation; Quadrature amplitude modulation; System testing; Viterbi algorithm;
fLanguage
English
Publisher
ieee
Conference_Titel
Consumer Electronics (ICCE), 2010 Digest of Technical Papers International Conference on
Conference_Location
Las Vegas, NV
Print_ISBN
978-1-4244-4314-7
Electronic_ISBN
978-1-4244-4316-1
Type
conf
DOI
10.1109/ICCE.2010.5418684
Filename
5418684
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