High-performance systolic arrays for band matrix multiplication

Author

Yang, Yun ; Zhao, Wenqing ; Inoue, Yasuaki

Author_Institution

Graduate Sch. of Inf., Waseda Univ., Kitakyushu, Japan

fYear

2005

fDate

23-26 May 2005

Firstpage

1130

Abstract

Band matrix multiplication is widely used in DSP systems. However, for band matrix multiplication, the traditional Kung-Leiserson systolic array cannot be realized with high cell-efficiency. Three high-performance band matrix multiplication systolic arrays (BMMSA) are presented, based on the ideas of "matrix compression" and "super pipelining". These new systolic arrays are realized by compressing the data matrix skillfully and adjusting the operating sequence carefully. The results show that the best systolic array for band matrix multiplication uses almost 100% of the processing elements (PE) in each step. Also, these modifications increase the operation speed, and, at best spend, only 1/3 of the processing time is required to complete the multiplication operation.

Keywords

data compression; digital signal processing chips; matrix multiplication; parallel processing; pipeline processing; signal processing; systolic arrays; DSP systems; Kung-Leiserson systolic array; band matrix multiplication; cell-efficiency; high-performance systolic arrays; matrix compression; parallel operation; super pipelining; Application specific integrated circuits; Computer architecture; Concurrent computing; Delay; Digital signal processing; Microelectronics; Production systems; Systolic arrays; Throughput; Yarn; band matrix multiplication; cell-efficiency; operation speed; parallel operation; systolic array;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on

Print_ISBN

0-7803-8834-8

Type

conf

DOI

10.1109/ISCAS.2005.1464792

Filename

1464792