Design of a new sense amplifier flip-flop with improved power-delay-product

Author

Zhang, Hui ; Mazumder, Pinaki

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA

fYear

2005

fDate

23-26 May 2005

Firstpage

1262

Abstract

A new sense-amplifier based flip-flop (SAFF) is proposed to improve the transition delay and to reduce the power consumption in comparison to those of existing SAFF designs. The speed improvement of the proposed SAFF is achieved by reducing the delay of the holding stage as well as the delay of the sampling stage. Power consumption is reduced by introducing a novel conditional precharge technique. The performance of the proposed flip-flop is simulated in SPICE with 0.18 μm CMOS technology. A performance comparison with existing SAFF designs is also included in this paper. The comparison results show considerable power-delay-product (PDP) improvement of the proposed SAFF design at low input signal switching activity.

Keywords

CMOS logic circuits; flip-flops; low-power electronics; 0.18 micron; CMOS; SAFF; holding stage delay reduction; power consumption reduction; power-delay-product improvement; precharge logic; sampling stage delay; sense-amplifier based flip-flop; transition delay; CMOS technology; Clocks; Delay; Energy consumption; Flip-flops; Latches; Power amplifiers; SPICE; Sampling methods; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on

Print_ISBN

0-7803-8834-8

Type

conf

DOI

10.1109/ISCAS.2005.1464824

Filename

1464824